1. Field of the Invention
This invention relates to a semiconductor package having heat sink at the outer surface, and more particularly to a semiconductor package having heat sink at the outer surface that can enhance the heat-dissipating effect.
2. Description of Related Art
Following the evolution of the integrated circuit technology, the manufacturing process of integrated circuit has been advanced to ever high in integration with a target of pursuing ever dense on the design of the package structure for the packaging process in the back end process. Owing to the demand of high speed on the data processing, the signal frequency of semiconductor devices is getting higher and higher. Together with the increase in the integration of semiconductor and the package density, the heat generation per unit time per unit volume has increased significantly. Therefore, just how to provide the semiconductor package with even more effective heat-dissipating path has become an important issue in order to improve the performance of the semiconductor devices.
FIG. 1 is a schematic cross-sectional view of a semiconductor package according to a prior art. As shown in FIG. 1, the package structure shown in FIG. 1 has been disclosed in the U.S. Pat. No. 5,252,783 (Motorola, 1993), and U.S. Pat. No. 5,594,234 (TI, 1997). The semiconductor package disclosed in these two patents is constructed on a lead frame and is having a die pad 102 surrounded by a plurality of leads 108. The die pad 102 has a top surface 104 and a bottom surface 106. The lead 108 has an inner lead portion 110 and an outer lead portion 112. The chip 114 has its back surface 118 bonded to the die pad 102 by the use of an adhesive 122. The bonding pads 120 on the active surface 116 of the chip 114 are electrically connected to the inner lead portion 110 of the leads 108 by the use of bonding wires 124. A molding compound 126 encapsulate the chip 114, the die pad 102, and the inner lead portion 110 of the leads 108 so as to constitute a package structure 100 that has a top surface 130 and a bottom surface 132. In order to facilitate the subsequent SMT (surface mount technology) process, the lead 108 has its outer lead portion 112 exposed at the side edge of the package structure 100 which is bent toward the bottom surface 132 and extended outward to form a gull wing.
The method to improve the heat-dissipating efficiency of the foregoing conventional semiconductor package is to expose the bottom surface 106 of the die pad 102 on the bottom surface of the package structure 100. However, those who is skilled in the art will readily observe that the heat is mainly generated on the active surface 116 and the heat is generally dissipated from the active surface 116 too. The conventional path of heat dissipation from the active surface 116 through the silicon base of the chip 114 and the die pad 102 is rather long. And since the thermal resistance of the silicon base of the chip 114 is rather high, thereby, the heat-dissipating efficiency by transferring the heat from the above-mentioned path of heat-dissipating is rather low. Therefore, the conventional package structure is unable to dissipate the heat effectively, as a result, the performance of the electronic devices will be affected.
Therefore, it is an objective of the present invention to provide a semiconductor package to improve the heat-dissipating efficiency of the package.
It is another objective of the present invention to provide a semiconductor package that can easily add an external heat dissipator in order to improve the heat-dissipating efficiency of the package further.
It is one other objective of the present invention to provide a semiconductor package having stacked chips in order to improve the heat-dissipating efficiency of the package and to enhance the performance of the electronic devices.
In order to attain the foregoing and other objectives, the present invention provides a semiconductor package having heat sink at the outer surface that is constructed on a lead frame. The package comprises a chip, a die pad, a plurality of leads, a plurality of bonding wires, and a molding compound. The die pad has a first surface and a second surface, and the chip has its active surface bonded to the first surface of the die pad. The area of the die pad is smaller than the area of the chip in order to expose the bonding pads on the active surface of the chip. The leads having an inner lead portions and an outer lead portions are disposed at the periphery of the die pad, and the inner lead portions are electrically connected to the bonding pads by a plurality of bonding wires. The molding compound encapsulates the chip, the die pad, the inner lead portions of the leads, and the bonding wires. The second surface of the die pad is exposed on the top surface of the package structure while the outer lead portion of the leads is exposed at the side edge of the package structure.
According to a preferred embodiment of the present invention, a heat sink and an external heat dissipator can be added to further improve the package""s heat-dissipating efficiency. The heat sink is bonded to the back surface of the chip while exposed on the bottom surface of the package structure. And the external heat dissipator is mounted on the exposed surface of the die pad.
Furthermore, in order to attain the foregoing and other objectives, the present invention also provides stacked-chip semiconductor package having heat sink at the outer surface. The stacked-chip semiconductor package comprises a first chip, a second chip, a die pad, a plurality of leads, a plurality of bonding wires, and a molding compound. The first chip has a first active surface and a first back surface wherein the first active surface comprises a plurality of first bonding pads. The second chip has a second active surface and a second back surface wherein the second active surface comprises a plurality of second bonding pads. The first chip has its first back surface bonded to the second back surface of the second chip. The die pad has a first surface and a corresponding second surface wherein the area of the die pad is smaller than the area of the first chip. The die pad has its first surface bonded to the first active surface of the first chip while the first bonding pads on the first active surface of the first chip are exposed. The leads are disposed at the periphery of the die pad, and each of the leads has an inner lead portion and an outer lead portion. The bonding wires electrically connect the first bonding pads to the first surface of the inner lead portion of the leads, and electrically connect the second bonding pads to the second surface of the inner lead portion of the leads. The molding compound encapsulates the first chip, the second chip, the die pad, the inner lead portion of the leads, and the bonding wires to form a package structure. The package structure comprises a first side and a second side wherein the die pad has the second surface exposed on the top surface of the package structure while the outer lead portion of the leads is exposed at the edge of the package structure.
According to another preferred embodiment of the present invention, a heat sink and an external heat dissipator can be added to the stacked chip package to further improve the package""s heat-dissipating efficiency. The heat sink is bonded to the active surface of the second chip while exposed on the bottom surface of the package structure. And the external heat dissipator is mounted on the exposed second surface of the die pad.